Modeling and Simulation of Operational Amplifier Using Verilog -ams

This paper puts forward a method of building a macro model of operational amplifier. And then it describes the way on how to use the Verilog-AMS language with the Cadence Virtuoso AMS simulator as a simulation tool in the behavior level. In order to verify the correctness of the behavior descriptions, the paper simulates the described op-amp in a basic integral operation. The result shows the macro model has appropriate accuracy while needs more less simulation time. The high-level model described by VerilogAMS has advantages in not only reducing simulation time but also simplifying the simulation process. The method that uses macro model for simulation of the more complex system will become wide spread in system design in the future.